Redundant memory lines are often used in semiconductor memory arrays to prevent an isolated cell defect from rendering an entire array unusable and thereby reducing processing yield. During the normal operation of a memory array without cell defects, master enable fuses for redundant memory lines remain intact thereby preventing the generation of master enable signals for associated redundant decoder circuits, which accordingly remain inactive. However, during electrical test after wafer processing, cell defects may be discovered and identified by location. Defective cells may be disconnected from the memory array by blowing fuses which may be, for example, laser blown fuses, current blown fuses or the like. Redundant memory line decoder circuits may be then enabled by blowing master enable fuses associated with a particular redundant row or column decoder using, for example, a laser device. By blowing master enable fuses, enable circuits may be configured to generate enable signals for redundant line decoder circuitry. Accordingly, addresses of defective cells are remapped to redundant memory lines through redundant decoders which have been enabled in the manner described above and which is described in greater detail in U.S. Pat. No. 5,568,061, previously cited.
Problems arise, however, initializing master enable circuits in semiconductor memory arrays which use redundancy control logic. In memory arrays, particularly those which provide for battery back-up, current related anomalies may arise. Excess current may be drawn, for example, by inactive master enable circuits which are subjected to initialization nonetheless. Other factors leading to excess current consumption and improper operation include, for example, indeterminate states in master enable circuit latches, and battery currents generated when portions of a memory array are powered by an external voltage supply operating at intermediate voltage levels and other portions are powered by a voltage supply which is switched from external voltage to battery voltage.
Master enable fuse circuitry is frequently associated with sequential logic for setting proper voltage and/or logic levels in related circuits, for example redundant memory line decoder circuits. As a result of the use of sequential logic however, the state of the logic circuitry associated with a blown master enable fuse can be indeterminate when power is initially applied during, for example, initial power up. Previous master enable fuse circuits have relied on junction leakage currents to eventually drag latch input nodes to a known state. However, master enable fuses which retain a slight conduction path even after being blown may prevent leakage giving rise to indeterminate states for latch inputs. Indeterminate states within integrated circuits can result in parts which are unreliable or unstable and which dissipate excessive power. Such anomalies may lead to shortened back-up battery life and/or excess current consumption during normal memory operation leading to crowbarring of circuit elements. Excess current consumption is particularly troublesome in parts which are rated for power efficiency.
Moreover, in prior art memory array circuits, critical memory cell circuitry for non-volatile memory devices has been powered by a "switched" voltage bus. The switched bus, which is powered by an external voltage supply, e.g. external Vcc, during power up, switches to battery power during power down transitions when the externally supplied voltage level drops below a critical voltage level. By providing battery back up in such a manner, memory cell contents are protected from degradation or alteration during power down. In order to conserve battery power, however, non-critical related circuits are not typically configured for battery back up giving rise to the need for multiple power busses throughout the part. The additional busses increase costs and complexity of manufacture for the part.
Master enable circuits have previously been powered by external Vcc and initialized with a signal having a voltage level such that, for inactive master enable circuits, e.g. circuits with the master enable fuse intact, the initialization signal caused current to be drawn from Vcc for the inactive master enable circuit during normal operation of the memory array.
It would be desirable therefore for a circuit and method for minimizing excess currents associated with fused master enable circuitry in integrated circuits and ensuring fused master enable circuits are in the proper initial states at power up from battery or external voltage supplies. It would further be desirable for such a circuit and method which minimizes the number of power busses throughout the integrated circuit.